As a processor technology develops, there has arisen a need for providing a reliable and fast way to write data into caches so as to allow for increased speed and performance of the total system. A typical processor performs two functions related to memory: it reads data from the memory, and writes data into the memory. There are several types of memories that processors utilize within a computer system: the main memory, dynamic random access memory (DRAM), and caches.
Retrieving information from the main disk memory generally takes the longest amount of time because hundreds of megabytes of information must be scanned to determine the location of information that was to be read or written. DRAMs are next in the amount of time required for access Although they are smaller than the main memory and therefore not so much information needs to be scanned for access, there are still four or more wait states required before the information can be accessed.
Hence, a cache is the memory that is utilized most often to access data to be utilized by the processor in the computer system. The problem with a cache, however, is that it is very small, usually hundreds of kilobytes of data; and therefore, there is a significant chance that instead of a "hit" during access, there will be a "miss" because the data required will not be available in the cache. What is done, then, is to write data from the main memory or the DRAM, as appropriate, into the cache so that the next time the data needs to be retrieved, it can be read from the cache by the processor.
However, in some processors, such as the Intel Corporation 486 processor, there is only a small window of time that a "write hit" can occur. What is meant by "write hit" is that time which is available to write data into the cache. In that particular processor, data can only be written into the cache during a 14 nanosecond (ns.) interval (49-63 ns.). That period of time is very small and will require a very fast static asynchronous Random access Memory (SRAM) or a synchronous SRAM to act as the cache. SRAMs of either of these types are expensive because oftentimes they must be smaller die size and the overall yields of SRAMS are very low. For example, the speed required to be able to directly access the memory during that 14 ns. hit period would require an SRAM that would be two to three times more expensive than the SRAM of average speed.
Hence, what is needed is a system in which the data can be written into a cache in a time interval that will allow the processor to read that information without inserting any wait states and also without requiring a fast SRAM. In addition, the system should not significantly add to the cost and complexity of the computer system.